| Free 64-bit single-core OpenSPARC processor core emerges |
Sep. 07, 2006
 A team of former STMicroelectronics engineers in Italy and Britain has created a single-core version of Sun's 8-way, 64-bit, GPL-licensed OpenSPARC T1 processor core. Simply RISC's free, open "S1" core can run Ubuntu Linux, and targets embedded devices such as PDAs, set-top boxes, and digital cameras, the company says.
Version 0.1 of the S1 core design can be freely downloaded, without registration, and simulated and synthesized using a Linux host and free verilog tools, the company says. Commercial simulation and synthesis tools from Synopsys also work with the design, the company says.
The S1 core design is based on the OpenSparc T1 design released by Sun under the GPL license in May. Sun apparently released the T1 design in hopes of increasing the number of embedded designs based on Solaris, as well as to inspire more Linux-based embedded designs based on the SPARC architecture.
While the T1 released by Sun has eight cores, the S1 design is based on a single CPU core "extracted" from the OpenSPARC T1 design, Simply RISC says, along with a reset controller and interrupt controller.
S1's fancy architecture diagram
(Source: Simply RISC)
The S1 design also includes a Wishbone bridge, rather than the "PCX/CPX" (processor-to-cache and vice-versa crossbar switch) used in the T1. Compatibility with the Wishbone specification maintained by OpenCores.org ensures that the S1 design can be combined with other Wishbone-friendly cores available through OpenCores.org, Simply RISC says.
The S1's core "basically" implements the SPARC v9 64-bit ISA (instruction set architecture), Simply RISC says. The company refer users to documentation "freely available on the opensparc.net" website for specifics.
A GCC compiler is available for the SPARC v9 ISA architecture, and x86-to-SPARC cross-development toolchains can be downloaded from the Internet, Simply RISC says.
Additionally, the SPARC v9 ISA is supported by the newest Linux kernel, and by various Linux software packages, according to the company. And, a version of the complete Ubuntu distribution available for the multi-core T1 "could be used in a seamless way also" for the S1 core, Simply RISC suggests.
Simply RISC spokesperson Fabrizio Fazzini said, "One of the main purposes was to keep the S1 Core environment as simple as possible to encourage developers: most of the simulation and synthesis activities are now performed with simple push-button scripts and system requirements are very easy to meet. Simply RISC plans to add new features to the S1 Core and test them extensively over the next months with the help of the community."
Simply RISC describes itself as a team of former STMicroelectronics engineers working in Catania, Italy and Bristol, UK. The company plans to develop and support GPL-licensed "CPU cores, peripherals, and interfaces," it says, in order to "build up free hardware design of microprocessors, Systems-on-a-Chip (SoC), and Networks-on-a-Chip (NoC)." The S1 is Simply RISC's first released design.
Availability
The initial 0.1 release of the S1 core is available now, and can be downloaded without registration. It requires a Linux system with bash and sed to install. For simulation, it requires Icarus Verilog (free software) or Synopsys VCS MX (commercial software). It can be synthesized using Icarus Verilog (free software) or Synopsys Design Compiler (commercial software), Simply RISC says.
The distribution may also work on Windows/Cygwin, according to the company, although this is untested.
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