| Chip startup talks up high efficiency Power designs |
Oct. 24, 2005
A microprocessor startup announced a family of energy-efficient Power architecture-based SoCs (system-on-chips) targeting embedded and high-performance computing applications, at the Fall Processor Forum in San Jose this week. PA Semiconductor says its first PWRficient chip, a dual-core model expected in 2006, will dissipate just 25 Watts at 2GHz.
PA Semiconductor has 150 employees, and was founded in 2003. It has been operating in "stealth mode" for three years, it says. It claims to employ "key designers" of defining architectures, including x86-64, Opteron, Itanium, and UltraSPARC.
 PA is led by Dan Dobberpuhl (pictured at right), a former VP of broadband processors at Broadcom, and a 20-year veteran of DEC's Alpha chip design team. Doberpuhl also led development of StrongARM and SiByte processors, PA says.
Power-based core
PA's PWRficient chips will be based on a "PA6T" core implemented from scratch using the 64-bit Power architecture, which PA licenses from IBM. The core is capable of 64-bit or 32-bit operation, and includes an FPU (floating point unit) and a VMX (SIMD vector unit). A superscalar, out-of-order design will deliver "triple-issue" performance, capable of executing three instructions per clock cycle, the company claims.
Additionally, the core has "built-in" virtualization support, the company says.
Chips based on the PA6T core will have integral northbridges, southbridges, and memory controllers, an approach that saves energy, while increasing throughputs and reducing latency, the company says. It expects to ship the first single-chip chipsets -- or "platform processors" as it calls them -- in their class.
Another small US-based processor team, Via's Centaur division, expects to sample an x86-based single chip PC design later this year.
First PA Semi chip
PA expects to sample its first product in the fourth quarter of 2006. The 1682M will be a dual-core, cache-coherent model clocked at 1.5 or 2GHz, and targeting network, security, datacenter, and storage appliances.
Built on 65nm process technology, the 1682M will feature 2MB of L2 cache, dual memory controllers, 24 Serdes lanes, eight PCI Express engines, and four SGMII Ethernet MACs.
PA6T-1682M architecture diagram
The company hopes typical power dissipation for the 1682M will run between 5 and 13 Watts, when clocked at 2GHz, with a maximum dissipation of 25 Watts -- well under the 95 Watts that some current PowerPC designs can dissipate, it says.
Roadmap
Other products and planned sample dates include:- Q1, 2007 -- Single-core processor targeting printing, imaging and client devices
- Q3, 2007 -- 4-core model targeting high-performance embedded
- Q2, 2008 -- 8-core model targeting supercomputers and super-servers
PA's PA6T-based chips will use one of three different socket pin-outs, providing a degree of design flexibility and an upgrade path for its customers, the company says.
PA Semi chips will use one of three socket definitions
Dobberpuhl said, "We had to start from scratch, rethinking every step, to achieve our breakthrough performance-per-Watt design. The result is a paradigm-shifting processor that has been enthusiastically received."
He adds, "As a founding member of Power.org, our plan is to foster an evolving partnership with IBM and the Power community."
Power.org VP of semiconductor products, Tom Reeves, said, "Helping to facilitate this type of innovation by P.A. Semi in Power Architecture is exactly why we created Power.org."
IBM launched power.org and the Power architecture's "Linux-like" licensing model on April Fools Day, 2004, at a "Power Everywhere" event in New York City.
LinuxDevices.com's annual survey for 2005 suggested that PowerPC is the third most popular -- and the fastest growing -- embedded architecture, behind ARM and x86.
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